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The L2 TLB structure is shared by instruction and data. It handles misses from the instruction and data L1 TLBs.
The following table describes the characteristic that applies to the L2 TLB.
Table A5-3 Characteristic of the L2 TLB
|5-way, set associative, 1280-entry cache||
Access to the L2 TLB usually takes three cycles. If a different page or block size mapping is used, then access to the L2 TLB can take longer.
The L2 TLB supports four translation table walks in parallel (four TLB misses), and can service two TLB lookups while the translation table walks are in progress. If there are six successive misses, the L2 TLB will stall.