D8.4 AMCFGR_EL0, Activity Monitors Configuration Register, EL0

The AMCFGR_EL0 provides information on the number of activity counters implemented and their size.

Bit field descriptions

The AMCFGR_EL0 is a 32-bit register.

Figure D8-1 AMCFGR_EL0 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


RES0, [31:14]
Reserved, RES0.
SIZE, [13:8]

Size of counters, minus one.

This field defines the size of the largest counter implemented by the activity monitors. In the Armv8-A architecture, the largest counter has 64 bits, therefore the value of this field is 0b111111.

N, [7:0]
Number of activity counters implemented, where the number of counters is N+1. The Cortex®‑A76 core implements five counters, therefore the value is 0x04.
Configurations
There are no configuration notes.

Usage constraints

Accessing the AMCFGR_EL0

To access the AMCFGR_EL0:

MRS <Xt>, AMCFGR_EL0 ; Read AMCFGR_EL0 into Xt

Register access is encoded as follows:

Table D8-4 AMCFGR_EL0 encoding

op0 op1 CRn CRm op2
11 011 1111 1010 110

The AMCFGR_EL0 can be accessed through the external debug interface, offset 0xE00. In this case, it is read-only.

This register is accessible as follows:

EL0 EL1 EL2 EL3
RO RO RO RO
Traps and enables

If ACTLR_EL2.AMEN is 0, then Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.

If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped to EL3.

If AMUSERENR_EL0.EN is 0, then accesses to this register from EL0 are trapped to EL1.

Non-ConfidentialPDF file icon PDF version100798_0400_00_en
Copyright © 2016–2019 Arm Limited or its affiliates. All rights reserved.