D4.3 PMCEID1, Performance Monitors Common Event Identification Register 1

The PMCEID1 defines which common architectural and common microarchitectural feature events are implemented.

Bit field descriptions

Figure D4-2 PMCEID1 bit assignments
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RES0, [31:24]
res0Reserved.
ID[55:32], [23:0]

Common architectural and microarchitectural feature events that can be counted by the PMU event counters.

For each bit described in the following table, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0.

Table D4-3 PMU common events

Bit Event mnemonic Description
[23] LL_CACHE_MISS_RD Attributable Last Level cache memory read miss.
1This event is implemented.
[22] LL_CACHE_RD Attributable Last Level cache memory read.
1This event is implemented.
[21] ITLB_WALK Attributable instruction TLB access with at least one translation table walk.
1This event is implemented.
[20] DTLB_WALK Attributable data or unified TLB access with at least one translation table walk.
1This event is implemented.
[17] REMOTE_ACCESS Attributable access to another socket in a multi-socket system.
1This event is implemented.
[15] L2D_TLB Attributable Level 2 data or unified TLB access.
1This event is implemented.
[13] L2D_TLB_REFILL Attributable Level 2 data or unified TLB refill.
1This event is implemented.
[11] L3D_CACHE Attributable Level 3 data cache access.
1This event is implemented.
[10] L3D_CACHE_REFILL Attributable Level 3 data cache refill.
1This event is implemented.
[9] L3D_CACHE_ALLOCATE Attributable Level 3 data or unified cache allocation without refill.
1This event is implemented.
[6] L1I_TLB Attributable Level 1 instruction TLB access.
1This event is implemented.
[5] L1D_TLB Attributable Level 1 data or unified TLB access.
1This event is implemented.
[4] STALL_BACKEND No operation issued due to backend.
1This event is implemented.
[3] STALL_FRONTEND No operation issued due to frontend.
1This event is implemented.
[2] BR_MIS_PRED_RETIRED Instruction architecturally executed, mispredicted branch.
1This event is not implemented.
[1] BR_RETIRED Instruction architecturally executed, branch.
1This event is implemented.
[0] L2D_CACHE_ALLOCATE Level 2 data cache allocation without refill.
1This event is implemented.

Note:

The PMU events implemented in the above table can be found in Table   C2-1 PMU Events.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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