A1.2 Features

The Cortex®‑A76 core includes the following features:

Core features

  • Full implementation of the Armv8.2-A A64, A32, and T32 instruction sets.
  • Armv8.4 Dot Product instruction support.
  • AArch32 execution state at Exception level EL0 only. AArch64 execution state at all Exception levels (EL0 to EL3).
  • Support for Arm TrustZone® technology.
  • A Memory Management Unit (MMU).
  • Superscalar, variable-length, out-of-order pipeline.
  • 40-bit Physical Address (PA).
  • An integrated execution unit that implements the Advanced SIMD and floating-point architecture support.
  • Optional Cryptographic Extension.
  • Generic Interrupt Controller (GICv4) CPU interface to connect to an external distributor.
  • Generic Timers interface supporting 64-bit count input from an external system counter.
  • Reliability, Availability, and Serviceability (RAS) Extension.
  • Support for Page Based Hardware Attributes (PBHA).

Cache features

  • Separate L1 data and instruction caches.
  • Private, unified data and instruction L2 cache.
  • Optional L1 and L2 memory protection in the form of Error Correcting Code (ECC) or parity on all RAM instances.

Debug features

  • Armv8.2 debug logic.
  • Performance Monitor Unit (PMU).
  • Embedded Trace Macrocell (ETM) that supports instruction trace only.
  • Activity Monitor Unit (AMU).
  • Optional Coresight Embedded Logic Analyzer (ELA).

See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.

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