B2.3 AArch64 implementation defined register summary

This section describes the AArch64 registers in the Cortex®‑A76 core that are implementation defined.

The following tables lists the AArch 64 implementation defined registers, sorted by opcode.

Table B2-3 AArch64 implementation defined registers

Name Copro CRn Op1 CRm Op2 Width Description
ATCR_EL1 3 c15 0 c7 0 32

B2.18 ATCR_EL1, Auxiliary Translation Control Register, EL1

ATCR_EL2 3 c15 4 c7 0 32 B2.19 ATCR_EL2, Auxiliary Translation Control Register, EL2
ATCR_EL12 3 c15 5 c7 0 32 B2.20 ATCR_EL12 , Alias to Auxiliary Translation Control Register EL1
ATCR_EL3 3 c15 6 c7 0 32 B2.21 ATCR_EL3, Auxiliary Translation Control Register, EL3
AVTCR_EL2 3 c15 4 c7 1 32 B2.22 AVTCR_EL2, Auxiliary Virtualized Translation Control Register, EL2
CPUACTLR_EL1 3 c15 0 c1 0 64 B2.28 CPUACTLR_EL1, CPU Auxiliary Control Register, EL1
CPUACTLR2_EL1 3 c15 0 c1 1 64 B2.29 CPUACTLR2_EL1, CPU Auxiliary Control Register 2, EL1
CPUACTLR3_EL1 3 c15 0 c1 2 64 B2.30 CPUACTLR3_EL1, CPU Auxiliary Control Register 3, EL1
CPUCFR_EL1 3 c15 0 c0 0 32 B2.31 CPUCFR_EL1, CPU Configuration Register, EL1
CPUECTLR_EL1 3 c15 0 c1 4 64 B2.32 CPUECTLR_EL1, CPU Extended Control Register, EL1
CPUPCR_EL3 3 c15 6 c8 1 64 B2.33 CPUPCR_EL3, CPU Private Control Register, EL3
CPUPMR_EL3 3 c15 6 c8 3 64 B2.34 CPUPMR_EL3, CPU Private Mask Register, EL3
CPUPOR_EL3 3 c15 6 c8 2 64 B2.35 CPUPOR_EL3, CPU Private Operation Register, EL3
CPUPSELR_EL3 3 c15 6 c8 0 32 B2.36 CPUPSELR_EL3, CPU Private Selection Register, EL3
CPUPWRCTLR_EL1 3 c15 0 c2 7 32 B2.37 CPUPWRCTLR_EL1, Power Control Register, EL1
ERXPFGCDN_EL1 3 c15 0 c2 2 32 B2.49 ERXPFGCDN_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1
ERXPFGCTL_EL1 3 c15 0 c2 1 32 B2.50 ERXPFGCTL_EL1, Selected Error Pseudo Fault Generation Control Register, EL1
ERXPFGF_EL1 3 c15 0 c2 0 32 B2.51 ERXPFGF_EL1, Selected Pseudo Fault Generation Feature Register, EL1

The following table shows the 32-bit wide implementation defined Cluster registers. Details of these registers can be found in Arm® DynamIQ™ Shared Unit Technical Reference Manual

Table B2-4 Cluster registers

Name Copro CRn Opc1 CRm Opc2 Width Description
CLUSTERCFR_EL1 3 c15 0 c3 0 32-bit Cluster configuration register.
CLUSTERIDR_EL1 3 c15 0 c3 1 32-bit Cluster main revision ID.
CLUSTEREVIDR_EL1 3 c15 0 c3 2 32-bit Cluster ECO ID.
CLUSTERACTLR_EL1 3 c15 0 c3 3 32-bit Cluster auxiliary control register.
CLUSTERECTLR_EL1 3 c15 0 c3 4 32-bit Cluster extended control register.
CLUSTERPWRCTLR_EL1 3 c15 0 c3 5 32-bit Cluster power control register.
CLUSTERPWRDN_EL1 3 c15 0 c3 6 32-bit Cluster power down register.
CLUSTERPWRSTAT_EL1 3 c15 0 c3 7 32-bit Cluster power status register.
CLUSTERTHREADSID_EL1 3 c15 0 c4 0 32-bit Cluster thread scheme ID register.
CLUSTERACPSID_EL1 3 c15 0 c4 1 32-bit Cluster ACP scheme ID register.
CLUSTERSTASHSID_EL1 3 c15 0 c4 2 32-bit Cluster stash scheme ID register.
CLUSTERPARTCR_EL1 3 c15 0 c4 3 32-bit Cluster partition control register.
CLUSTERBUSQOS_EL1 3 c15 0 c4 4 32-bit Cluster bus QoS control register.
CLUSTERL3HIT_EL1 3 c15 0 c4 5 32-bit Cluster L3 hit counter register.
CLUSTERL3MISS_EL1 3 c15 0 c4 6 32-bit Cluster L3 miss counter register.
CLUSTERTHREADSIDOVR_EL1 3 c15 0 c4 7 32-bit Cluster thread scheme ID override register
CLUSTERPMCR_EL1 3 c15 0 c5 0 32-bit Cluster Performance Monitors Control Register
CLUSTERPMCNTENSET_EL1 3 c15 0 c5 1 32-bit Cluster Count Enable Set Register
CLUSTERPMCNTENCLR_EL1 3 c15 0 c5 2 32-bit Cluster Count Enable Clear Register
CLUSTERPMOVSSET_EL1 3 c15 0 c5 3 32-bit Cluster Overflow Flag Status Set
CLUSTERPMOVSCLR_EL1 3 c15 0 c5 4 32-bit Cluster Overflow Flag Status Clear
CLUSTERPMSELR_EL1 3 c15 0 c5 5 32-bit Cluster Event Counter Selection Register
CLUSTERPMINTENSET_EL1 3 c15 0 c5 6 32-bit Cluster Interrupt Enable Set Register
CLUSTERPMINTENCLR_EL1 3 c15 0 c5 7 32-bit Cluster Interrupt Enable Clear Register
CLUSTERPMXEVTYPER_EL1 3 c15 0 c6 1 32-bit Cluster Selected Event Type and Filter Register
CLUSTERPMXEVCNTR_EL1 3 c15 0 c6 2 32-bit Cluster Selected Event Counter Register
Reserved/RAZ 3 c15 0 c6 3 32-bit Cluster Monitor Debug Configuration Register
CLUSTERPMCEID0_EL1 3 c15 0 c6 4 32-bit Cluster Common Event Identification ID0 Register
CLUSTERPMCEID1_EL1 3 c15 0 c6 5 32-bit Cluster Common Event Identification ID1 Register
CLUSTERPMCLAIMSET_EL1 3 c15 0 c6 6 32-bit Cluster Performance Monitor Claim Tag Set Register
CLUSTERPMCLAIMCLR_EL1 3 c15 0 c6 7 32-bit Cluster Performance Monitor Claim Tag Clear Register
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