A6.6.3 Encoding for the L2 unified cache

The following tables show the encoding required to select a given cache line.

Table A6-22 L2 tag location encoding

Bit fields of Rd Description
[31:24] RAMID = 0x10
[23:21] Reserved
[20:18] Way (0->7)
[17:16] Reserved
[15:6] Index[15:6]
[5:0] Reserved

Table A6-23 L2 data location encoding

Bit fields of Rd Description
[31:24] RAMID = 0x11
[23:21] Reserved
[20:18] Way (0->7)
[17:16] Reserved
[15:4] Index[15:4]
[3:0] Reserved

Table A6-24 L2 victim location encoding

Bit fields of Rd Description
[31:24] RAMID = 0x12
[23:16] Reserved
[15:6] Index[15:6]
[5:0] Reserved

The following table shows the data that is returned from accessing the L2 tag RAM when L2 is configured with a 128KB cache size.

Table A6-25 L2 tag format with a 128KB L2 cache size

Register Bit field Description
CORE_PBHA=FALSE CORE_PBHA=TRUE
Data Register 0

[63:45]

[63:47] 0
[44:38] [46:40] ECC [6:0] if configured with ECC for a 128KB L2 cache size, otherwise 0
- [39:38] PBHA [1:0]
[37:12] [37:12]

Physical address [39:14]

[11] [11] Non-secure identifier for the physical address
[10:9] [10:9] Virtual index [13:12]
[8:6] [8:6] Reserved
[5] [5] Shareable
[4] [4] Outer allocation hint
[3] [3] L1 data cache valid
[2:0] [2:0]

L2 State

101Modified
001Exclusive
x11Shared
xx0Invalid
Data Register 1 [63:0] [63:0] 0
Data Register 2 [63:0] [63:0] 0

The following table shows the data that is returned from accessing the L2 tag RAM when L2 is configured with a 256KB cache size.

Table A6-26 L2 tag format with a 256KB L2 cache size

Register Bit field Description
CORE_PBHA=FALSE CORE_PBHA=TRUE
Data Register 0 [63:44] [63:46] 0
[43:37] [45:39] ECC [6:0] if configured with ECC for a 256KB L2 cache size, otherwise 0
- [38:37] PBHA [1:0]
[36:12] [36:12]

Physical address [39:15]

[11] [11] Non-secure identifier for the physical address
[10:9] [10:9] Virtual index [13:12]
[8:6] [8:6] Reserved
[5] [5] Shareable
[4] [4] Outer allocation hint
[3] [3] L1 data cache valid
[2:0] [2:0]

L2 State

101Modified
001Exclusive
x11Shared
xx0Invalid
Data Register 1 [63:0] [63:0] 0
Data Register 2 [63:0] [63:0] 0

The following table shows the data that is returned from accessing the L2 tag RAM when L2 is configured with a 512KB cache size.

Table A6-27 L2 tag format with a 512KB L2 cache size

Register Bit field Description
CORE_PBHA=FALSE CORE_PBHA=TRUE
Data Register 0 [63:43] [63:45] 0
[42:36] [44:38] ECC [6:0] if configured with ECC for a 512KB L2 cache size, otherwise 0
- [37:36] PBHA [1:0]
[35:12] [35:12]

Physical address [39:16]

[11] [11] Non-secure identifier for the physical address
[10:9] [10:9] Virtual index [13:12]
[8:6] [8:6] Reserved
[5] [5] Shareable
[4] [4] Outer allocation hint
[3] [3] L1 data cache valid
[2:0] [2:0]

L2 State

101Modified
001Exclusive
x11Shared
xx0Invalid
Data Register 1 [63:0] [63:0] 0
Data Register 2 [63:0] [63:0] 0

The following table shows the data that is returned from accessing the L2 data RAM.

Table A6-28 L2 data format

Register Bit field Description
Data Register 0 [63:0] Data [63:0]
Data Register 1 [63:0] Data [127:64]
Data Register 2 [63:16] 0
[15:8] ECC for Data [127:64] if configured with ECC
[7:0] ECC for Data [63:0] if configured with ECC

The following table shows the data that is returned from accessing the L2 victim RAM.

Table A6-29 L2 victim format

Register Bit field Description
Data Register 0 [63:7] 0
[6:0] PLRU [6:0]
Data Register 1 [63:0] 0
Data Register 2 [63:0] 0
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