B2.62 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1

The ID_AA64ISAR0_EL1 provides information about the instructions implemented in AArch64 state, including the instructions that are provided by the Cryptographic Extension.

Bit field descriptions

ID_AA64ISAR0_EL1 is a 64-bit register, and is part of the Identification registers functional group.

This register is Read Only.

The optional Cryptographic Extension is not included in the base product of the core. Arm requires licensees to have contractual rights to obtain the Cryptographic Extension.

Figure B2-45 ID_AA64ISAR0_EL1 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


RES0, [63:48]
RES0Reserved.
DP, [47:44]

Indicates whether Dot Product support instructions are implemented.

0x1UDOT, SDOT instructions are implemented.
RES0, [43:32]
RES0Reserved.
RDM, [31:28]

Indicates whether SQRDMLAH and SQRDMLSH instructions in AArch64 are implemented.

0x1SQRDMLAH and SQRDMLSH instructions implemented.
RES0, [27:24]
RES0Reserved.
Atomic, [23:20]

Indicates whether Atomic instructions in AArch64 are implemented. The value is:

0x2

LDADD, LDCLR, LDEOR, LDSET, LDSMAX, LDSMIN, LDUMAX, LDUMIN, CAS, CASP, and SWP instructions are implemented

.
CRC32, [19:16]

Indicates whether CRC32 instructions are implemented. The value is:

0x1CRC32 instructions are implemented.
SHA2, [15:12]

Indicates whether SHA2 instructions are implemented. The possible values are:

0x0No SHA2 instructions are implemented. This is the value if the core implementation does not include the Cryptographic Extension.
0x1SHA256H, SHA256H2, SHA256U0, and SHA256U1 implemented. This is the value if the core implementation includes the Cryptographic Extension.
SHA1, [11:8]

Indicates whether SHA1 instructions are implemented. The possible values are:

0x0No SHA1 instructions implemented. This is the value if the core implementation does not include the Cryptographic Extension.
0x1SHA1C, SHA1P, SHA1M, SHA1SU0, and SHA1SU1 implemented. This is the value if the core implementation includes the Cryptographic Extension.
AES, [7:4]

Indicates whether AES instructions are implemented. The possible values are:

0x0No AES instructions implemented. This is the value if the core implementation does not include the Cryptographic Extension.
0x2AESE, AESD, AESMC, and AESIMC implemented, plus PMULL and PMULL2 instructions operating on 64-bit data. This is the value if the core implementation includes the Cryptographic Extension.
[3:0]
Reserved, RES0.
Configurations

ID_AA64ISAR0_EL1 is architecturally mapped to external register ID_AA64ISAR0.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Non-ConfidentialPDF file icon PDF version100798_0400_00_en
Copyright © 2016–2019 Arm Limited or its affiliates. All rights reserved.