D9.1 Memory-mapped AMU register summary

The AMU registers are accessible through the external debug interface.

The memory-mapped AMU registers are listed in the following table. For those registers not described in this chapter, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Table D9-1 Memory-mapped AMU register summary

Offset Name Type Description
0xC20 AMCNTENCLR_EL0 RO D8.2 AMCNTENCLR_EL0, Activity Monitors Count Enable Clear Register, EL0
0xC00 AMCNTENSET_EL0 RO D8.3 AMCNTENSET_EL0, Activity Monitors Count Enable Set Register, EL0
0xE00 AMCFGR_EL0 RO D8.4 AMCFGR_EL0, Activity Monitors Configuration Register, EL0

[63:32]: 0x004+8n

[31:0]: 0x000+8n

AMEVCNTRn_EL0 RO D8.6 AMEVCNTRn_EL0, Activity Monitor Event Counter Register, EL0
0x400+4n AMEVTYPERn_EL0 RO D8.7 AMEVTYPERn_EL0, Activity Monitor Event Type Register, EL0

Note:

AMUSERENR_EL0 is excluded from the memory mapped view.
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