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The core is part of a debug system and supports both self-hosted and external debug.
The following figure shows a typical external debug system.
The lowest level of the system implements system support for the protocol converter to access the debug unit using the Advanced Peripheral Bus (APB) slave interface. An example of a debug target is a development system with a test chip or a silicon part with a core.
Helps debugging software that is running on the core:
With the debug unit, you can:
For self-hosted debug, the debug target runs additional debug monitor software that runs on the Cortex®‑A76 core itself. This way, it does not require expensive interface hardware to connect a second host computer.