C1.2.3 Effects of resets on debug registers

The core has the following reset signals that affect the debug registers:

nCPUPORESET
This signal initializes the core logic, including the debug, ETM trace unit, breakpoint, watchpoint logic, and performance monitors logic. This maps to a Cold reset that covers reset of the core logic and the integrated debug functionality.
nCORERESET
This signal resets some of the debug and performance monitor logic. This maps to a Warm reset that covers reset of the core logic.
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