D3.1 Memory-mapped debug register summary

The following table shows the offset address for the registers that are accessible from the external debug interface.

For those registers not described in this chapter, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Table D3-1 Memory-mapped debug register summary

Offset Name Type Width Description
0x000-0x01C - - - Reserved
0x020 EDESR RW 32 External Debug Event Status Register
0x024 EDECR RW 32 External Debug Execution Control Register
0x028-0x02C - - - Reserved
0x030 EDWAR[31:0] RO 64 External Debug Watchpoint Address Register
0x034 EDWAR[63:32]
0x038-0x07C - - - Reserved
0x080 DBGDTRRX_EL0 RW 32 Debug Data Transfer Register, Receive
0x084 EDITR WO 32 External Debug Instruction Transfer Register
0x088 EDSCR RW 32

External Debug Status and Control Register

0x08C DBGDTRTX_EL0 WO 32 Debug Data Transfer Register, Transmit
0x090 EDRCR WO 32 D3.14 EDRCR, External Debug Reserve Control Register
0x094 - RW 32 Reserved
0x098 EDECCR RW 32 External Debug Exception Catch Control Register
0x09C - - - Reserved
0x0A0 - - -

Reserved

0x0A4 - - - Reserved
0x0A8 - - - Reserved
0x0AC - - -

Reserved

0x0B0-0x2FC - - - Reserved
0x300 OSLAR_EL1 WO 32 OS Lock Access Register
0x304-0x30C - - - Reserved
0x310 EDPRCR RW 32 External Debug Power/Reset Control Register
0x314 EDPRSR RO 32

External Debug Processor Status Register

0x318-0x3FC - - - Reserved
0x400 DBGBVR0_EL1[31:0] RW 64 Debug Breakpoint Value Register 0
0x404 DBGBVR0_EL1[63:32]
0x408 DBGBCR0_EL1 RW 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
0x40C - - - Reserved
0x410 DBGBVR1_EL1[31:0] RW 64 Debug Breakpoint Value Register 1
0x414 DBGBVR1_EL1[63:32]
0x418 DBGBCR1_EL1 RW 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
0x41C - - - Reserved
0x420 DBGBVR2_EL1[31:0] RW 64 Debug Breakpoint Value Register 2
0x424 DBGBVR2_EL1[63:32]
0x428 DBGBCR2_EL1 RW 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
0x42C - - - Reserved
0x430 DBGBVR3_EL1[31:0] RW 64 Debug Breakpoint Value Register 3
0x434 DBGBVR3_EL1[63:32]
0x438 DBGBCR3_EL1 RW 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
0x43C - - - Reserved
0x440 DBGBVR4_EL1[31:0] RW 64 Debug Breakpoint Value Register 4
0x444 DBGBVR4_EL1[63:32]
0x448 DBGBCR4_EL1 RW 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
0x44C - - - Reserved
0x450 DBGBVR5_EL1[31:0] RW 64 Debug Breakpoint Value Register 5
0x454 DBGBVR5_EL1[63:32]
0x458 DBGBCR5_EL1 RW 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
0x45C-0x7FC - - - Reserved
0x800 DBGWVR0_EL1[31:0] RW 64 Debug Watchpoint Value Register 0
0x804 DBGWVR0_EL1[63:32]
0x808 DBGWCR0_EL1 RW 32 D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
0x80C - - - Reserved
0x810 DBGWVR1_EL1[31:0] RW 64 Debug Watchpoint Value Register 1
0x814 DBGWVR1_EL1[63:32]
0x818 DBGWCR1_EL1 RW 32 D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
0x81C - - - Reserved
0x820 DBGWVR2_EL1[31:0] RW 64 Debug Watchpoint Value Register 2
0x824 DBGWVR2_EL1[63:32]
0x828 DBGWCR2_EL1 RW 32 D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
0x82C - - - Reserved
0x830 DBGWVR3_EL1[31:0] RW 64 Debug Watchpoint Value Register 0,
0x834 DBGWVR3_EL1[63:32]
0x838 DBGWCR3_EL1 RW 32 D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
0x83C-0xCFC - - - Reserved
0xD00 MIDR RO 32 B2.90 MIDR_EL1, Main ID Register, EL1
0xD04-0xD1C - - - Reserved
0xD20 EDPFR[31:0] RO 64 B2.67 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
0xD24 EDPFR[63:32]
0xD28 EDDFR[31:0] RO 64 B2.67 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
0xD2C EDDFR[63:32]
0xD60-0xEFC - - - Reserved
0xF00 - - - Reserved
0xF04-0xF9C - - - Reserved
0xFA0 DBGCLAIMSET_EL1 RW 32 D2.3 DBGCLAIMSET_EL1, Debug Claim Tag Set Register, EL1
0xFA4 DBGCLAIMCLR_EL1 RW 32 Debug Claim Tag Clear Register
0xFA8 EDDEVAFF0 RO 32

External Debug Device Affinity Register 0

0xFAC EDDEVAFF1 RO 32 External Debug Device Affinity Register 1
0xFB0 - - -

Reserved

0xFB4 - - - Reserved
0xFB8 DBGAUTHSTATUS_EL1 RO 32

Debug Authentication Status Register

0xFBC EDDEVARCH RO 32 External Debug Device Architecture Register
0xFC0 EDDEVID2 RO 32 External Debug Device ID Register 2, res0
0xFC4 EDDEVID1 RO 32 D3.7 EDDEVID1, External Debug Device ID Register 1
0xFC8 EDDEVID RO 32 D3.6 EDDEVID, External Debug Device ID Register 0
0xFCC EDDEVTYPE RO 32

External Debug Device Type Register

0xFD0 EDPIDR4 RO 32 D3.12 EDPIDR4, External Debug Peripheral Identification Register 4
0xFD4-0xFDC EDPIDR5-7 RO 32 D3.13 EDPIDRn, External Debug Peripheral Identification Registers 5-7
0xFE0 EDPIDR0 RO 32 D3.8 EDPIDR0, External Debug Peripheral Identification Register 0
0xFE4 EDPIDR1 RO 32 D3.9 EDPIDR1, External Debug Peripheral Identification Register 1
0xFE8 EDPIDR2 RO 32 D3.10 EDPIDR2, External Debug Peripheral Identification Register 2
0xFEC EDPIDR3 RO 32 D3.11 EDPIDR3, External Debug Peripheral Identification Register 3
0xFF0 EDCIDR0 RO 32 D3.2 EDCIDR0, External Debug Component Identification Register 0
0xFF4 EDCIDR1 RO 32 D3.3 EDCIDR1, External Debug Component Identification Register 1
0xFF8 EDCIDR2 RO 32 D3.4 EDCIDR2, External Debug Component Identification Register 2
0xFFC EDCIDR3 RO 32 D3.5 EDCIDR3, External Debug Component Identification Register 3
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