A4.6.5 Debug recovery mode

The debug recovery mode can be used to assist debug of external watchdog-triggered reset events.

It allows contents of the core L1 data cache that was present before the reset to be observable after the reset. The contents of the L1 cache are retained and are not altered on the transition back to the On mode.

By default, the core invalidates its caches when power-on reset (nCPUPORESET) is deasserted. If the P-Channel is initialized to the debug recovery mode, and the core is cycled through power-on reset along with the system power-on reset, then the cache invalidation is disabled. The cache contents are preserved when the core is transitioned to the On mode.

Debug recovery mode also supports preserving RAS state, in addition to the cache contents. In this case, a transition to the debug recovery mode is made from any of the current states. Once in debug recovery mode, the core is cycled through a warm reset with the system warm reset. The RAS and cache state are preserved when the core is transitioned to the On mode.

This mode is strictly for debug purposes. It must not be used for functional purposes, as correct operation of the L1 cache is not guaranteed when entering this mode.


This mode can occur at any time with no guarantee of the state of the core. A P-Channel request of this type is accepted immediately, therefore its effects on the core, cluster, or the wider system are unpredictable, and a wider system reset might be required. In particular, if there were outstanding memory system transactions at the time of the reset, then these may complete after the reset when the core is not expecting them and cause a system deadlock.
Non-ConfidentialPDF file icon PDF version100798_0400_00_en
Copyright © 2016–2019 Arm Limited or its affiliates. All rights reserved.