|Home > Register descriptions > AArch64 system registers > ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2, EL1|
The ID_AA64MMFR2_EL1 provides information about the implemented memory model and memory management support in the AArch64 Execution state.
ID_AA64MMFR2_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Indicates support for a larger virtual address. The value is:
|VMSAv8-64 supports 48-bit virtual addresses.|
Indicates whether an implicit Error Synchronization Barrier has been inserted. The value is:
Indicates whether LDM and STM ordering control bits are supported. The value is:
|LSMAOE and nTLSMD bit not supported.|
Indicates the presence of the User Access Override (UAO). The value is:
|UAO is supported.|
Common not Private. Indicates whether a TLB entry is pointed at a translation table base register that is a member of a common set. The value is:
|CnP bit is supported.|
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.