B2.49 ERXPFGCDN_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1

Register ERXPFGCDN_EL1 accesses the ERR<n>PFGCND register for the error record selected by ERRSELR_EL1.SEL.

If ERRSELR_EL1.SEL==0, then ERXPFGCDN_EL1 accesses the ERR0PFGCDN register of the core error record. See B3.7 ERR0PFGCDN, Error Pseudo Fault Generation Count Down Register.

If ERRSELR_EL1.SEL==1, then ERXPFGCDN_EL1 accesses the ERR1PFGCDNR register of the DSU error record. See the Arm® DynamIQ™ Shared Unit Technical Reference Manual.


There are no configuration notes.

Accessing the ERXPFGCDN_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>,<systemreg>

This register can be written using MSR with the following syntax:

MSR <Xt>,<systemreg>

This syntax is encoded with the following settings in the instruction encoding:

<systemreg> op0 op1 CRn CRm op2
S3_0_C15_C2_2 11 000 1111 0010 010

This register is accessible in software as follows:

<syntax> Control Accessibility
S3_0_C15_C2_2 x x 0 - RW n/a RW
S3_0_C15_C2_2 x 0 1 - RW RW RW
S3_0_C15_C2_2 x 1 1 - n/a RW RW
n/aNot accessible. Executing the PE at this Exception level is not permitted.
Traps and enables

For a description of the prioritization of any generated exceptions, see Exception priority order in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for exceptions taken to AArch32 state, and see Synchronous exception prioritization for exceptions taken to AArch64 state. Subject to these prioritization rules, the following traps and enables are applicable when accessing this register.

ERXPFGCDN_EL1 is accessible at EL3 and can be accessible at EL1 and EL2 depending on the value of bit[5] in ACTLR_EL2 and ACTLR_EL3. See B2.6 ACTLR_EL2, Auxiliary Control Register, EL2 and B2.7 ACTLR_EL3, Auxiliary Control Register, EL3.


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