|Home > Register descriptions > AArch64 system registers > CPUCFR_EL1, CPU Configuration Register, EL1|
The CPUCFR_EL1 provides configuration information for the core.
CPUCFR_EL1 is a 32-bit register, and is part of the IMPLEMENTATION DEFINED registers functional group.
This register is Read Only.
Indicates whether ECC is present or not. The possible values are:
|ECC is not present.|
|ECC is present.|
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
This register can be read with the MRS instruction using the following syntax:
To access the CPUCFR_EL1:
MRS <Xt>, CPUCFR_EL1 ; Read CPUCFR_EL1 into Xt
This syntax is encoded with the following settings in the instruction encoding:
This register is accessible in software as follows:
'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible.