|Home > Register descriptions > AArch64 system registers > AFSR1_EL3, Auxiliary Fault Status Register 1, EL3|
AFSR1_EL3 provides additional IMPLEMENTATION DEFINED fault status information for exceptions that are taken to EL3. This register is not used in the Cortex®‑A76 core.
AFSR1_EL3 is a 32-bit register, and is part of:
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.