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The ERR0STATUS contains information about the error record.
The register indicates:
ERR0STATUS is a 32-bit register.
Address Valid. The possible values are:
|ERR0ADDR is not valid.|
ERR0ADDR contains an address associated with the highest priority error recorded by this record.
Status Register valid. The possible values are:
|ERR0STATUS is not valid.|
|ERR0STATUS is valid. At least one error has been recorded.|
No error that could not be corrected or deferred has been detected.
|At least one error that could not be corrected or deferred has been detected. If error recovery interrupts are enabled, then the interrupt signal is asserted until this bit is cleared.|
|No external abort has been reported.|
|The node has reported an external abort to the master that is in access or making a transaction.|
|More than one error has occurred and so details of the other error have been discarded.|
ERR0MISC0 and ERR0MISC1 are not valid.
|This bit indicates that ERR0MISC0 contains additional information about any error that is recorded by this record.|
|No corrected error recorded.|
|At least one corrected error recorded.|
|No errors were deferred.|
|At least one error was not corrected and deferred by poisoning.|
Poison. The value is:
The Cortex®‑A76 core cannot distinguish a poisoned value from a corrupted value.
|Errors due to fault injection.|
|ECC error from internal data buffer.|
|ECC error on cache data RAM.|
|ECC error on cache tag or dirty RAM.|
|Parity error on TLB data RAM.|
Error response for a cache copyback.
Deferred error from slave not supported at the consumer. For example, poisoned data received from a slave by a master that cannot defer the error further.
There are no configuration notes.
ERR0STATUS resets to
ERR0STATUS is accessible from the following registers when ERRSELR.SEL==0: