|Home > Register descriptions > AArch64 system registers > CPTR_EL3, Architectural Feature Trap Register, EL3|
The CPTR_EL3 controls trapping to EL3 of access to CPACR_EL1, CPTR_EL2, trace functionality and registers associated with Advanced SIMD and floating-point execution.
It also controls EL3 access to trace functionality and registers associated with Advanced SIMD and floating-point execution.
CPTR_EL3 is a 32-bit register, and is part of the Security registers functional group.
Trap Trace Access.
Not implemented. RES0.
Traps all accesses to SVE, Advanced SIMD and floating-point functionality to EL3. This applies to all Exception levels, both Security states, and both Execution states. The possible values are:
|Does not cause any instruction to be trapped. This is the reset value.|
|Any attempt at any Exception level to execute an instruction that uses the registers that are associated with SVE, Advanced SIMD and floating-point is trapped to EL3, subject to the exception prioritization rules.|
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.