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The CTR_EL0 provides information about the architecture of the caches.
CTR_EL0 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Data cache clean requirements for instruction to data coherence:
| ||Data cache clean to the point of unification is required for instruction to data coherence, unless CLIDR_EL1.LoC == 0b000 or (CLIDR_EL1.LoUIS == 0b000 && CLIDR_EL1.LoUU == 0b000). .|
| ||Data cache clean to the point of unification is not required for instruction to data coherence.|
IDC reflects the inverse value of the BROADCASTCACHEMAINTPOU pin.
Cache write-back granule. Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified:
||Cache write-back granule size is 16 words.|
Exclusives Reservation Granule. Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions:
||Exclusive reservation granule size is 16 words.|
Log2 of the number of words in the smallest cache line of all the data and unified caches that the core controls:
||Smallest data cache line size is 16 words.|
Instruction cache policy. Indicates the indexing and tagging policy for the L1 Instruction cache:
| ||Physically Indexed Physically Tagged (PIPT).|
Log2 of the number of words in the smallest cache line of all the instruction caches that the core controls.
||Smallest instruction cache line size is 16 words.|
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.