|Home > Register descriptions > AArch64 system registers > ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0, EL1|
The ID_AFR0_EL1 provides information about the IMPLEMENTATION DEFINED features of the PE in AArch32. This register is not used in the Cortex®‑A76 core.
ID_AFR0_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.