D6.9 PMPIDR2, Performance Monitors Peripheral Identification Register 2

The PMPIDR2 provides information to identify a Performance Monitor component.

Bit field descriptions

The PMPIDR2 is a 32-bit register.

Figure D6-8 PMPIDR2 bit assignments
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RES0, [31:8]
res0Reserved.
Revision, [7:4]
0x4

r4p0.

JEDEC, [3]
0b1RAO. Indicates a JEP106 identity code is used.
DES_1, [2:0]
0b011Arm Limited. This is the most significant nibble of JEP106 ID code.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The PMPIDR2 can be accessed through the external debug interface, offset 0xFE8.

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