D6.4 PMCIDR1, Performance Monitors Component Identification Register 1

The PMCIDR1 provides information to identify a Performance Monitor component.

Bit field descriptions

The PMCIDR1 is a 32-bit register.

Figure D6-3 PMCIDR1 bit assignments
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RES0, [31:8]
res0Reserved.
CLASS, [7:4]
0x9Debug component.
PRMBL_1, [3:0]
0x0Preamble byte 1.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The PMCIDR1 can be accessed through the external debug interface, offset 0xFF4.

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