D10.68 TRCSTATR, Status Register

The TRCSTATR indicates the ETM trace unit status.

Bit field descriptions

The TRCSTATR is a 32-bit register.

Figure D10-64 TRCSTATR bit assignments
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RES0, [31:2]
res0Reserved.
PMSTABLE, [1]

Indicates whether the ETM trace unit registers are stable and can be read:

0The programmers model is not stable.
1The programmers model is stable.
IDLE, [0]

Idle status:

0The ETM trace unit is not idle.
1The ETM trace unit is idle.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCSTATR can be accessed through the external debug interface, offset 0x00C.

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