D10.20 TRCCONFIGR, Trace Configuration Register

The TRCCONFIGR controls the tracing options.

Bit field descriptions

The TRCCONFIGR is a 32-bit register.

Figure D10-19 TRCCONFIGR bit assignments
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RES0, [31:18]
res0Reserved.
DV, [17]

Enables data value tracing. The possible values are:

0Disables data value tracing.
1Enables data value tracing.
DA, [16]

Enables data address tracing. The possible values are:

0Disables data address tracing.
1Enables data address tracing.
VMIDOPT, [15]

Configures the Virtual context identifier value used by the trace unit, both for trace generation and in the Virtual context identifier comparators. The possible values are:

0b0VTTBR_EL2.VMID is used. If the trace unit supports a Virtual context identifier larger than the VTTBR_EL2.VMID, the upper unused bits are always zero. If the trace unit supports a Virtual context identifier larger than 8 bits and if the VTCR_EL2.VS bit forces use of an 8-bit Virtual context identifier, bits [15:8] of the trace unit Virtual context identifier are always zero.
0b1CONTEXTIDR_EL2 is used. TRCIDR2.VMIDOPT indicates whether this field is implemented.
QE, [14:13]

Enables Q element. The possible values are:

0b00Q elements are disabled.
0b01Q elements with instruction counts are disabled. Q elements without instruction counts are disabled.
0b10Reserved.
0b11Q elements with and without instruction counts are enabled.
RS, [12]

Enables the return stack. The possible values are:

0Disables the return stack.
1Enables the return stack.
TS, [11]

Enables global timestamp tracing. The possible values are:

0Disables global timestamp tracing.
1Enables global timestamp tracing.
COND, [10:8]

Enables conditional instruction tracing. The possible values are:

0b000Conditional instruction tracing is disabled.
0b001Conditional load instructions are traced.
0b010Conditional store instructions are traced.
0b011Conditional load and store instructions are traced.
0b111All conditional instructions are traced.
VMID, [7]

Enables VMID tracing. The possible values are:

0Disables VMID tracing.
1Enables VMID tracing.
CID, [6]

Enables context ID tracing. The possible values are:

0Disables context ID tracing.
1Enables context ID tracing.
RES0, [5]
res0Reserved.
CCI, [4]

Enables cycle counting instruction trace. The possible values are:

0Disables cycle counting instruction trace.
1Enables cycle counting instruction trace.
BB, [3]

Enables branch broadcast mode. The possible values are:

0Disables branch broadcast mode.
1Enables branch broadcast mode.
INSTP0, [2:1]

Controls whether load and store instructions are traced as P0 instructions. The possible values are:

0b00Load and store instructions are not traced as P0 instructions.
0b01Load instructions are traced as P0 instructions.
0b10Store instructions are traced as P0 instructions.
0b11Load and store instructions are traced as P0 instructions.
RES1, [0]
res1Reserved.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCCONFIGR can be accessed through the external debug interface, offset 0x010.

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