D10.27 TRCEVENTCTL1R, Event Control 1 Register

The TRCEVENTCTL1R controls the behavior of the events that TRCEVENTCTL0R selects.

Bit field descriptions

The TRCEVENTCTL1R is a 32-bit register.

Figure D10-24 TRCEVENTCTL1R bit assignments
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RES0, [31:13]
res0Reserved.
LPOVERRIDE, [12]

Low-power state behavior override:

0Low-power state behavior unaffected.
1Low-power state behavior overridden. The resources and Event trace generation are unaffected by entry to a low-power state.
ATB, [11]

ATB trigger enable:

0ATB trigger disabled.
1ATB trigger enabled.
RES0, [10:4]
res0Reserved.
EN, [3:0]

One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs:

0Event does not cause an event element.
1Event causes an event element.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCEVENTCTL1R can be accessed through the external debug interface, offset 0x024.

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