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The TRCEVENTCTL1R controls the behavior of the events that TRCEVENTCTL0R selects.
The TRCEVENTCTL1R is a 32-bit register.
Low-power state behavior override:
|Low-power state behavior unaffected.|
|Low-power state behavior overridden. The resources and Event trace generation are unaffected by entry to a low-power state.|
ATB trigger enable:
|ATB trigger disabled.|
|ATB trigger enabled.|
One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs:
|Event does not cause an event element.|
|Event causes an event element.|
Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.
The TRCEVENTCTL1R can be accessed through the external debug interface,