D10.67 TRCSTALLCTLR, Stall Control Register

The TRCSTALLCTLR enables the ETM trace unit to stall the Cortex®‑A76 core if the ETM trace unit FIFO overflows.

Bit field descriptions

The TRCSTALLCTLR is a 32-bit register.

Figure D10-63 TRCSTALLCTLR bit assignments
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RES0, [31:9]
res0Reserved.
ISTALL, [8]

Instruction stall bit. Controls if the trace unit can stall the core when the instruction trace buffer space is less than LEVEL:

0The trace unit does not stall the core.
1The trace unit can stall the core.
RES0, [7:4]
res0Reserved.
LEVEL, [3:2]

Threshold level field. The field can support 4 monotonic levels from 0b00 to 0b11, where:

0b00Zero invasion. This setting has a greater risk of an ETM trace unit FIFO overflow.
0b11Maximum invasion occurs but there is less risk of a FIFO overflow.
RES0, [1:0]
res0Reserved.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCSTALLCTLR can be accessed through the external debug interface, offset 0x02C.

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