D10.67 TRCSTALLCTLR, Stall Control Register
The TRCSTALLCTLR enables the ETM trace unit to stall the Cortex®‑A76 core if the ETM trace unit FIFO overflows.
Bit field descriptions
The TRCSTALLCTLR is a 32-bit register.
D10-63 TRCSTALLCTLR bit assignments
- RES0, [31:9]
- ISTALL, 
Instruction stall bit. Controls if the trace unit
can stall the core when the instruction trace buffer space is less than
|The trace unit does not stall the core.
|The trace unit can stall the core.
- RES0, [7:4]
- LEVEL, [3:2]
Threshold level field. The field can support 4
monotonic levels from
|Zero invasion. This setting has a greater risk of an ETM trace
unit FIFO overflow.
|Maximum invasion occurs but there is less risk of a FIFO
- RES0, [1:0]
Bit fields and details not provided in this description are
architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.
The TRCSTALLCTLR can be accessed through the external debug interface, offset