D10.72 TRCVICTLR, ViewInst Main Control Register

The TRCVICTLR controls instruction trace filtering.

Bit field descriptions

The TRCVICTLR is a 32-bit register.

Figure D10-68 TRCVICTLR bit assignments
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RES0, [31:24]
res0Reserved.
EXLEVEL_NS, [23:20]

In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level:

0Trace unit generates instruction trace, in Non-secure state, for Exception level n.
1

Trace unit does not generate instruction trace, in Non-secure state, for Exception level n.

The Exception levels are:

Bit[20]

Exception level 0.

Bit[21]Exception level 1.
Bit[22]Exception level 2.
Bit[23]RAZ/WI. Instruction tracing is not implemented for Exception level 3.
EXLEVEL_S, [19:16]

In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level:

0Trace unit generates instruction trace, in Secure state, for Exception level n.
1Trace unit does not generate instruction trace, in Secure state, for Exception level n.

The Exception levels are:

Bit[16]Exception level 0.
Bit[17]Exception level 1.
Bit[18]RAZ/WI. Instruction tracing is not implemented for Exception level 2.
Bit[19]Exception level 3.
RES0, [15:12]
res0Reserved.
TRCERR, [11]

Selects whether a system error exception must always be traced:

0System error exception is traced only if the instruction or exception immediately before the system error exception is traced.
1System error exception is always traced regardless of the value of ViewInst.
TRCRESET, [10]

Selects whether a reset exception must always be traced:

0Reset exception is traced only if the instruction or exception immediately before the reset exception is traced.
1Reset exception is always traced regardless of the value of ViewInst.
SSSTATUS, [9]

Indicates the current status of the start/stop logic:

0Start/stop logic is in the stopped state.
1Start/stop logic is in the started state.
RES0, [8]
res0Reserved.
TYPE, [7]

Selects the resource type for the viewinst event:

0Single selected resource.
1Boolean combined resource pair.
RES0, [6:4]
res0Reserved.
SEL, [3:0]

Selects the resource number to use for the viewinst event, based on the value of TYPE:

When TYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].

When TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCVICTLR can be accessed through the external debug interface, offset 0x080.

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