D10.63 TRCSEQRSTEVR, Sequencer Reset Control Register

The TRCSEQRSTEVR resets the sequencer to state 0.

Bit field descriptions

The TRCSEQRSTEVR is a 32-bit register

Figure D10-59 TRCSEQRSTEVR bit assignments
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RES0, [31:8]
res0Reserved.
RESETTYPE, [7]

Selects the resource type to move back to state 0:

0Single selected resource.
1Boolean combined resource pair.
RES0, [6:4]
res0Reserved.
RESETSEL, [3:0]

Selects the resource number, based on the value of RESETTYPE:

When RESETTYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].

When RESETTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCSEQRSTEVR can be accessed through the external debug interface, offset 0x118.

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