D10.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1

The TRCCNTRLDVRn define the reload value for the counter.

Bit field descriptions

The TRCCNTRLDVRn is a 32-bit register.

Figure D10-17 TRCCNTRLDVRn bit assignments
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RES0, [31:16]
res0Reserved.
VALUE, [15:0]
Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCCNTRLDVRn registers can be accessed through the external debug interface, offsets:

TRCCNTRLDVR0
0x140.
TRCCNTRLDVR1
0x144.
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