D10.17 TRCCNTCTLR1, Counter Control Register 1

The TRCCNTCTLR1 controls the counter.

Bit field descriptions

The TRCCNTCTLR1 is a 32-bit register.

Figure D10-16 TRCCNTCTLR1 bit assignments
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RES0, [31:18]
res0Reserved.
CNTCHAIN, [17]

Defines whether the counter decrements when the counter reloads. This enables two counters to be used in combination to provide a larger counter:

0The counter operates independently from the counter. The counter only decrements based on CNTTYPE and CNTSEL.
1The counter decrements when the counter reloads. The counter also decrements when the resource selected by CNTTYPE and CNTSEL is active.
RLDSELF, [16]

Defines whether the counter reloads when it reaches zero:

0The counter does not reload when it reaches zero. The counter only reloads based on RLDTYPE and RLDSEL.
1The counter reloads when it is zero and the resource selected by CNTTYPE and CNTSEL is also active. The counter also reloads based on RLDTYPE and RLDSEL.
RLDTYPE, [15]

Selects the resource type for the reload:

0Single selected resource.
1Boolean combined resource pair.
RES0, [14:12]
res0Reserved.
RLDSEL, [11:8]

Selects the resource number, based on the value of RLDTYPE:

When RLDTYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].

When RLDTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

CNTTYPE, [7]

Selects the resource type for the counter:

0Single selected resource.
1Boolean combined resource pair.
RES0, [6:4]
res0Reserved.
CNTSEL, [3:0]

Selects the resource number, based on the value of CNTTYPE:

When CNTTYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].

When CNTTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCCNTCTLR1 can be accessed through the external debug interface, offset 0x154.

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