|Home > Debug registers > ETM registers > TRCIMSPEC0, Implementation Specific Register 0|
The TRCIMSPEC0 shows the presence of any implementation specific features, and enables any features that are provided.
The TRCIMSPEC0 is a 32-bit register.
|No implementation specific extensions are supported.|
Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.
The TRCIMSPEC0 can be accessed through the external debug interface, offset