D10.30 TRCIDR1, ID Register 1

The TRCIDR1 returns the base architecture of the trace unit.

Bit field descriptions

The TRCIDR1 is a 32-bit register.

Figure D10-27 TRCIDR1 bit assignments
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DESIGNER, [31:24]

Indicates which company designed the trace unit:

0x41Arm.
RES0, [23:16]
res0Reserved.
RES1, [15:12]
res1Reserved.
TRCARCHMAJ, [11:8]

Major trace unit architecture version number:

0b0100ETMv4.
TRCARCHMIN, [7:4]

Minor trace unit architecture version number:

0x2ETMv4.2
REVISION, [3:0]

Trace unit implementation revision number:

0x4ETM revision for r4p0

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCIDR1 can be accessed through the external debug interface, offset 0x1E4.

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