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The TRCIDR3 indicates:
The TRCIDR3 is a 32-bit register.
Indicates whether TRCSTALLCTLR.NOOVERFLOW is implemented:
|TRCSTALLCTLR.NOOVERFLOW is not implemented.|
Indicates the number of cores available for tracing:
|The trace unit can trace one core, ETM trace unit sharing not supported.|
Indicates whether stall control is implemented:
|The system supports core stall control.|
Indicates whether TRCSTALLCTLR is implemented:
|TRCSTALLCTLR is implemented.|
This field is used in conjunction with SYSSTALL.
Indicates whether there is a fixed synchronization period:
|TRCSYNCPR is read-write so software can change the synchronization period.|
Indicates whether TRCVICTLR.TRCERR is implemented:
|TRCVICTLR.TRCERR is implemented.|
Each bit controls whether instruction tracing in Non-secure state is implemented for the corresponding Exception level:
|Instruction tracing is implemented for Non-secure EL0, EL1, and EL2 Exception levels.|
Each bit controls whether instruction tracing in Secure state is implemented for the corresponding Exception level:
|Instruction tracing is implemented for Secure EL0, EL1, and EL3 Exception levels.|
The minimum value that can be programmed in TRCCCCTLR.THRESHOLD:
|Instruction trace cycle counting minimum threshold is 4.|
Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.
The TRCIDR3 can be accessed through the external debug interface, offset