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The TRCSSCCR0 controls the single-shot comparator.
The TRCSSCSR0 is a 32-bit register
Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to be detected:
|Reset enabled. Multiple matches can occur.|
Selects one or more address range comparators for single-shot control.
One bit is provided for each implemented address range comparator.
Selects one or more single address comparators for single-shot control.
One bit is provided for each implemented single address comparator.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.
The TRCSSCCR0 can be accessed through the external debug interface, offset