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The TRCSSCSR0 indicates the status of the single-shot comparator. TRCSSCSR0 is sensitive to instruction addresses.
The TRCSSCSR0 is a 32-bit register
Single-shot status. This indicates whether any of the selected comparators have matched:
|Match has not occurred.|
|Match has occurred at least once.|
When programming the ETM trace unit, if TRCSSCCRn.RST is b0, the STATUS bit must be explicitly written to 0 to enable this single-shot comparator control.
Data value comparator support:
|Single-shot data value comparisons not supported.|
Data address comparator support:
|Single-shot data address comparisons not supported.|
Instruction address comparator support:
|Single-shot instruction address comparisons supported.|
Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.
The TRCSSCSR0 can be accessed through the external debug interface, offset