D10.51 TRCOSLSR, OS Lock Status Register

The TRCOSLSR returns the status of the OS Lock.

Bit field descriptions

The TRCOSLSR is a 32-bit register.

Figure D10-48 TRCOSLSR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


RES0, [31:4]
res0Reserved.
OSLM[1], [3]

OS Lock model [1] bit. This bit is combined with OSLM[0] to form a two-bit field that indicates the OS Lock model is implemented.

The value of this field is always 0b10, indicating that the OS Lock is implemented.

nTT, [2]
This bit is RAZ, that indicates that software must perform a 32-bit write to update the TRCOSLAR.
OSLK, [1]

OS Lock status bit:

0OS Lock is unlocked.
1OS Lock is locked.
OSLM[0], [0]

OS Lock model [0] bit. This bit is combined with OSLM[1] to form a two-bit field that indicates the OS Lock model is implemented.

The value of this field is always 0b10, indicating that the OS Lock is implemented.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCOSLSR can be accessed through the external debug interface, offset 0x304.

Non-ConfidentialPDF file icon PDF version100798_0400_00_en
Copyright © 2016–2019 Arm Limited or its affiliates. All rights reserved.