D10.52 TRCPDCR, Power Down Control Register

The TRCPDCR request to the system power controller to keep the ETM trace unit powered up.

Bit field descriptions

The TRCPDCR is a 32-bit register.

Figure D10-49 TRCPDCR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


RES0, [31:4]
res0Reserved.
PU, [3]

Powerup request, to request that power to the ETM trace unit and access to the trace registers is maintained:

0Power not requested.
1Power requested.

This bit is reset to 0 on a trace unit reset.

RES0, [2:0]
res0Reserved.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCPDCR can be accessed through the external debug interface, offset 0x310.

Non-ConfidentialPDF file icon PDF version100798_0400_00_en
Copyright © 2016–2019 Arm Limited or its affiliates. All rights reserved.