D10.8 TRCCIDCCTLR0, Context ID Comparator Control Register 0

The TRCCIDCCTLR0 controls the mask value for the context ID comparators.

Bit field descriptions

The TRCCIDCCTLR0 is a 32-bit register.

Figure D10-7 TRCCIDCCTLR0 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


RES0, [31:4]
res0Reserved.
COMP0, [3:0]

Controls the mask value that the trace unit applies to TRCCIDCVR0. Each bit in this field corresponds to a byte in TRCCIDCVR0. When a bit is:

0The trace unit includes the relevant byte in TRCCIDCVR0 when it performs the Context ID comparison.
1The trace unit ignores the relevant byte in TRCCIDCVR0 when it performs the Context ID comparison.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCCIDCCTLR0 can be accessed through the external debug interface, offset 0x680.

Non-ConfidentialPDF file icon PDF version100798_0400_00_en
Copyright © 2016–2019 Arm Limited or its affiliates. All rights reserved.