D10.42 TRCITATBIDR, Integration ATB Identification Register

The TRCITATBIDR sets the state of output pins, mentioned in the bit descriptions in this section.

Bit field descriptions

The TRCITATBIDR is a 32-bit register.

Figure D10-39 TRCITATBIDR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Reserved. Read undefined.
ID, [6:0]

Drives the ATIDMn[6:0] output pins.

When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The TRCITATBIDR bit values correspond to the physical state of the output pins.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCITATBIDR can be accessed through the external debug interface, offset 0xEE4.

Non-ConfidentialPDF file icon PDF version100798_0400_00_en
Copyright © 2016–2019 Arm Limited or its affiliates. All rights reserved.