D10.44 TRCITIATBINR, Integration Instruction ATB In Register

The TRCITIATBINR reads the state of the input pins described in this section.

Bit field descriptions

The TRCITIATBINR is a 32-bit register.

Figure D10-41 TRCITIATBINR bit assignments
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For all non-reserved bits:

  • When an input pin is LOW, the corresponding register bit is 0.
  • When an input pin is HIGH, the corresponding register bit is 1.
  • The TRCITIATBINR bit values always correspond to the physical state of the input pins.
Reserved. Read undefined.
Returns the value of the AFVALIDMn input pin.
Returns the value of the ATREADYMn input pin.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCITIATBINR can be accessed through the external debug interface, offset 0xEF4.

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