D10.44 TRCITIATBINR, Integration Instruction ATB In Register

The TRCITIATBINR reads the state of the input pins described in this section.

Bit field descriptions

The TRCITIATBINR is a 32-bit register.

Figure D10-41 TRCITIATBINR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


For all non-reserved bits:

  • When an input pin is LOW, the corresponding register bit is 0.
  • When an input pin is HIGH, the corresponding register bit is 1.
  • The TRCITIATBINR bit values always correspond to the physical state of the input pins.
[31:2]
Reserved. Read undefined.
AFVALIDM, [1]
Returns the value of the AFVALIDMn input pin.
ATREADYM, [0]
Returns the value of the ATREADYMn input pin.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCITIATBINR can be accessed through the external debug interface, offset 0xEF4.

Non-ConfidentialPDF file icon PDF version100798_0400_00_en
Copyright © 2016–2019 Arm Limited or its affiliates. All rights reserved.