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The TRCLAR controls access to registers using the memory-mapped interface, when PADDRDBG31 is LOW.
The TRCLAR is a 32-bit register.
Read-As-Zero, write ignore.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.
The TRCLAR can be accessed through the external debug interface, offset