D10.10 TRCCIDR0, ETM Component Identification Register 0

The TRCCIDR0 provides information to identify a trace component.

Bit field descriptions

The TRCCIDR0 is a 32-bit register.

Figure D10-9 TRCCIDR0 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


RES0, [31:8]
res0Reserved.
PRMBL_0, [7:0]
0x0DPreamble byte 0.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCCIDR0 can be accessed through the external debug interface, offset 0xFF0.

Non-ConfidentialPDF file icon PDF version100798_0400_00_en
Copyright © 2016–2019 Arm Limited or its affiliates. All rights reserved.