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The DISR_EL1 records the SError interrupts consumed by an
DISR_EL1 is a 64-bit register, and is part of the registers Reliability, Availability, Serviceability (RAS) functional group.
Set to 1 when ESB defers an asynchronous SError interrupt. If the implementation does not include any synchronizable sources of SError interrupt, this bit is res0.
Indicates the type of format the deferred SError interrupt uses. The value of this bit is:
Deferred error uses architecturally-defined format.
|Uncontainable error (UC).|
|Unrecoverable error (UEU).|
The recovery software must also examine any implemented fault records to determine the location and extent of the error.
Data Fault Status Code. The possible values of this field are:
Asynchronous SError interrupt.
Note:In AArch32 the
There are no configuration notes.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.