B3.7 ERR0PFGCDN, Error Pseudo Fault Generation Count Down Register

ERR0PFGCDN is the Cortex®‑A76 node register that generates one of the errors that are enabled in the corresponding ERR0PFGCTL register.

Bit field descriptions

ERR0PFGCDN is a 32-bit register and is RW.

Figure B3-5 ERR0PFGCDN bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

CDN, [31:0]
Count Down value. The reset value of the Error Generation Counter is used for the countdown.

There are no configuration options.


When ERRSELR.SEL==0, ERR0PFGCDN is accessible from B2.49 ERXPFGCDN_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1.

Non-ConfidentialPDF file icon PDF version100798_0400_00_en
Copyright © 2016–2019 Arm Limited or its affiliates. All rights reserved.