B2.100 TCR_EL2, Translation Control Register, EL2

The TCR_EL2 controls translation table walks required for stage 1 translation of a memory access from EL2 and holds cacheability and shareability information.

Bit field descriptions

TCR_EL2 is a 64-bit register.

TCR_EL2 is part of:

  • The Virtual memory control registers functional group.
  • The Hypervisor and virtualization registers functional group.
Figure B2-83 TCR_EL2 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Bits[28:21], architecturally defined, are implemented in the core.

HD, [22]

Dirty bit update. The possible values are:

0Dirty bit update is disabled.
1Dirty bit update is enabled.
HA, [21]

Stage 1 Access flag update. The possible values are:

0Stage 1 Access flag update is disabled.
1Stage 1 Access flag update is enabled.

When the Virtualization Host Extension is activated, TCR_EL2 has the same bit assignments as TCR_EL1.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Non-ConfidentialPDF file icon PDF version100798_0400_00_en
Copyright © 2016–2019 Arm Limited or its affiliates. All rights reserved.