|Home > Register descriptions > AArch64 system registers > TCR_EL3, Translation Control Register, EL3|
The TCR_EL3 controls translation table walks required for stage 1 translation of memory accesses from EL3 and holds cacheability and shareability information for the accesses.
TCR_EL3 is a 32-bit register and is part of the Virtual memory control registers functional group.
Bits[28:21], architecturally defined, are implemented in the core.
Dirty bit update. The possible values are:
|Dirty bit update is disabled.|
|Dirty bit update is enabled.|
Stage 1 Access flag update. The possible values are:
|Stage 1 Access flag update is disabled.|
|Stage 1 Access flag update is enabled.|
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.