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This section describes the RAS error types that are introduced by the RAS extension and supported in the Cortex®‑A76 core.
When a component accesses memory, an error might be detected in that memory and then be corrected, deferred, or detected but silently propagated. The following table lists the types of RAS errors that are supported in the Cortex‑A76 core.
Table A8-2 RAS error types supported in the Cortex‑A76 core
|RAS error type||Definition|
|Corrected||A Corrected Error (CE) is reported for a single-bit ECC error on any protected RAM.|
|Deferred||A Deferred Error (DE) is reported for a double-bit ECC error that affects the data RAM on either the L1 data cache or the L2 cache.|
|Uncorrected||An Uncorrected Error (UE) is reported for a double-bit ECC error that affects the tag RAM of either the L1 data cache or the L2 cache. An Uncorrected Error is also reported for external aborts received in response to a store, data cache maintenance, instruction cache maintenance, TLBI maintenance, or cache copyback of dirty data.|