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The MIDR_EL1 provides identification information for the core, including an implementer code for the device and a device ID number.
MIDR_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Indicates the implementer code. This value is:
||ASCII character 'A' - implementer is Arm® Limited.|
Indicates the variant number of the core. This is the major revision number x in the rx part of the rxpy description of the product revision status. This value is:
Indicates the architecture code. This value is:
||Defined by CPUID scheme.|
Indicates the primary part number. This value is:
| ||Cortex®‑A76 core.|
Indicates the minor revision number of the core. This is the minor revision number y in the py part of the rxpy description of the product revision status. This value is:
The MIDR_EL1 is architecturally mapped to external MIDR_EL1 register.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.