B2.19 ATCR_EL2, Auxiliary Translation Control Register, EL2

The ATCR_EL2 determines the values of PBHA on page table walks memory access in EL2 translation regime.

This register is only used when Page Based Hardware Attributes (PBHA) is configured by the core.

Bit field descriptions

ATCR_EL2 is a 64-bit register.

Figure B2-15 ATCR_EL2 bit assignments
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[63:14]
RES0.
HWVAL160, [13]
Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTBR1_EL2 if HWEN160 is set.
HWVAL159, [12]
Indicates the value of PBHA[0] on page table walks memory access targeting the base address defined by TTBR1_EL2 if HWEN159 is set.
[11:10]
RES0.
HWVAL060, [9]
Indicates the value of PBHA[1] page table walks memory access targeting the base address defined by TTBR0_EL2 if HWEN060 is set.
HWVAL059, [8]
Indicates the value of PBHA[1] page table walks memory access targeting the base address defined by TTBR0_EL2 if HWEN059 is set.
[7:6]
RES0.
HWEN160, [5]
Enables PBHA[1] page table walks memory access targeting the base address defined by TTBR1_EL2. If this bit is clear, PBHA[1] on page table walks is 0.
HWEN159, [4]
Enables PBHA[0] page table walks memory access targeting the base address defined by TTBR1_EL2. If this bit is clear, PBHA[0] on page table walks is 0.
[3:2]
RES0.
HWEN060, [1]
Enables PBHA[1] page table walks memory access targeting the base address defined by TTBR0_EL2. If this bit is clear, PBHA[1] on page table walks is 0.
HWEN059, [0]
Enables PBHA[0] page table walks memory access targeting the base address defined by TTBR0_EL2. If this bit is clear, PBHA[0] on page table walks is 0.
Configurations

AArch64 ATCR_EL2 register is architecturally mapped to AArch32 register AHTCR.

Usage constraints

Accessing the ATCR_EL2

To access the ATCR_EL2:

MRS Xt, S< 3   4  c15   c7  0> ; Read ATCR_EL2 into Xt  
MSR S < 3   4 c15   c7 0 > , Xt   ; Write Xt to ATCR_EL2

This syntax is encoded with the following settings in the instruction encoding:

Op0 Op1 CRn CRm Op2
3 4 c15 c7 0
Accessibility

ATCR_EL2 is accessible as follows:

EL0 (NS) EL1 (NS) EL1 (S) EL2 EL3 (SCR.NS=1) EL3 (SCR.NS=0)
- - - RW RW RW
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