B2.21 ATCR_EL3, Auxiliary Translation Control Register, EL3

The ATCR_EL3 determines the values of PBHA on page table walks memory access in EL3 translation regime.

This register is only used when Page Based Hardware Attributes (PBHA) is configured by the core.

Bit field descriptions

ATCR_EL3 is a 64-bit register.

Figure B2-16 ATCR_EL3 bit assignments
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[63:10]
RES0.
HWVAL60, [9]
Indicates the value of PBHA[1] page table walks memory access if HWEN60 is set.
HWVAL59, [8]
Indicates the value of PBHA[1] page table walks memory access if HWEN59 is set.
[7:2]
RES0.
HWEN60, [1]
Enables PBHA[1] page table walks memory access. If this bit is clear, PBHA[1] on page table walks is 0.
HWEN59, [0]
Enables PBHA[0] page table walks memory access. If this bit is clear, PBHA[0] on page table walks is 0.
Configurations

AArch64 register ATCR_EL3 is architecturally mapped to AArch32 register ATCR (S).

Usage constraints

Accessing the ATCR_EL3

To access the ATCR_EL3:

MRS Xt , < 3  6 c15  c7 0>  ; Read ATCR_EL3 into Xt 
MSR S < 3   6 c15   c7 0 > , Xt   ; Write Xt to ATCR_EL3

This syntax is encoded with the following settings in the instruction encoding:

Op0 Op1 CRn CRm Op2
3 6 c15 c7 0
Accessibility

ATCR_EL3 is accessible as follows:

EL0 EL1 (NS) EL1 (S) EL2 EL3 (SCR.NS=1) EL3 (SCR.NS=0)
- - - - RW RW
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